Mixed-Signal Front Ends (MxFE)

The AD9082 mixed signal front-end (MxFE^®) is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) core, and 12-bit, 6 GSPS maximum sample rate, RF analog-to-digital converter (ADC) cores. The AD9082 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) having wide instantaneous bandwidth. The device features eight transmit lanes and eight receive lanes that support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B standards. The device also has an on-chip clock multiplier and digital signal processing (DSP) capability targeted at either wideband or multiband, direct to RF applications. The DSP datapaths can be bypassed to allow a direct connection between the converter cores and the JESD204B/C data transceiver port. The device also features low latency loopback, frequency hopping modes, and datapath multiplexer (mux) configurations useful for phase array radar system and electronic warfare applications. Two models for the AD9082 are offered. The 4D2AC model supports four DACs and two ADCs. The 2D2AC model supports two DACs and two ADCs.

APPLICATIONS

• Wireless communications infrastructure
• Microwave point-to-point, E-band and 5G mmWave
• Broadband communications systems
• DOCSIS 3.1 and 4.0 CMTS
• Phased array radar and electronic warfare
• Electronic test and measurement systems

The AD9081 mixed signal front end (MxFE^®) is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The AD9081 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) that have wide instantaneous bandwidth. The device features eight transmit and eight receive lanes that support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B standards. The device also has an on-chip clock multiplier, and a digital signal processing (DSP) capability targeted at either wideband or multiband direct to RF applications. The DSP datapaths can be bypassed to allow a direct connection between the converter cores and the JESD204 data transceiver port. The device also features low latency loopback and frequency hopping modes targeted at phase array radar system and electronic warfare applications. Two models for the AD9081 are offered. The 4D4AC model supports the full instantaneous channel bandwidth, whereas the 4D4AB model supports a maximum instantaneous bandwidth of 600 MHz per channel by automatically configuring the DSP to limit the instantaneous bandwidth at startup.

APPLICATIONS

• Wireless communications infrastructure
• Microwave point-to-point, E-band and 5G mmWave
• Broadband communications systems
• DOCSIS 3.1 and 4.0 CMTS
• Phased array radar and electronic warfare
• Electronic test and measurement systems

The AD9861 is a member of the MxFE family—a group of integrated converters for the communications market. The AD9861 integrates dual 10-bit analog-to-digital converters (ADC) and dual 10-bit digital-to-analog converters (TxDAC^®). Two speed grades are available, -50 and -80. The -50 is optimized for ADC sampling of 50 MSPS and less, while the -80 is optimized for ADC sample rates between 50 MSPS and 80 MSPS. The dual TxDACs operate at speeds up to 200 MHz and include a bypassable 2× or 4× interpolation filter. Three auxiliary converters are also available to provide required system level control voltages or to monitor system signals. The AD9861 is optimized for high performance, low power, small form factor, and to provide a cost-effective solution for the broadband communication market.

The AD9861 uses a single input clock pin (CLKIN) to generate all system clocks. The ADC and TxDAC clocks are generated within a timing generation block that provides user programmable options such as divide circuits, PLL multipliers, and switches.

A flexible, bidirectional 20-bit I/O bus accommodates a variety of custom digital back ends or open market DSPs.

In half-duplex systems, the interface supports 20-bit parallel transfers or 10-bit interleaved transfers. In full-duplex systems, the interface supports an interleaved 10-bit ADC bus and an interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin count and, therefore, reduces the required package size on the AD9861 and the device to which it connects.

The AD9861 can use either mode pins or a serial programmable interface (SPI) to configure the interface bus, operate the ADC in a low power mode, configure the TxDAC interpolation rate, and control ADC and TxDAC power-down. The SPI provides more programmable options for both the TxDAC path (for example, coarse and fine gain control and offset control for channel matching) and the ADC path (for example, the internal duty cycle stabilizer, and twos complement data format).

The AD9861 is packaged in a 64-lead LFCSP (low profile, fine pitched, chip scale package). The 64-lead LFCSP footprint is only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into tightly spaced applications such as PCMCIA cards.

Applications

• Broadband access
• Broadband LAN
• Communications (modems)

The AD9868 is a mixed-signal front-end (MxFE^®) IC for transceiver applications requiring Tx path and Rx path functionality with data rates up to 80 MSPS. A lower cost, pin-compatible version of the AD9865, the AD9868 removes the current amplifier (IAMP) IOUTP functionality and limits the PLL VCO operating range of 80 MHz to 200 MHz.

The part is well-suited for half- and full-duplex applications. The digital interface is extremely flexible, allowing simple interfacing to digital back ends that support half- or full-duplex data transfers, often allowing the AD9868 to replace discrete ADC and DAC solutions. Power-saving modes include the ability to reduce power consumption of individual functional blocks or power down unused blocks in half-duplex applications. A serial port interface (SPI) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks, from a single crystal or clock source.

The Tx signal path consists of a 2x/4x low-pass interpolation filter, a 10-bit TxDAC, and a line driver. The transmit path signal bandwidth can be as high as 34 MHz at an input data rate of 80 MSPS. The TxDAC provides differential current outputs that can be steered directly to an external load or to an internal low distortion current amplifier (IAMP) capable of delivering 17 dBm peak signal power. Tx power can be digitally controlled over a 19.5 dB range in 0.5 dB steps.

The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC. The low noise RxPGA has a programmable gain range of −12 dB to +48 dB in 1 dB steps. Its input referred noise is less than 3 nV/√Hz for gain settings beyond 36 dB. The receive path LPF cutoff frequency can be set over a 15 MHz to 35 MHz range or it can be simply bypassed. The 10-bit ADC achieves excellent dynamic performance up to an 80 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization.

The AD9868 provides a highly integrated solution for many broadband modems. It is available in a space-saving package, a 16-lead LFCSP, and is specified over the commercial temperature range (−40°C to +85°C).

Applications

The AD9961/AD9963 are pin-compatible, 10-/12-bit, low power MxFE^® converters that provide two ADC channels with sample rates of 100 MSPS and two DAC channels with sample rates to 170 MSPS. These converters are optimized for transmit and receive signal paths of communication systems requiring low power and low cost. The digital interfaces provide flexible clocking options. The transmit is configurable for 1×, 2×, 4×, and 8× interpolation. The receive path has a bypassable 2× decimating low-pass filter.

The AD9961 and AD9963 have five auxiliary analog channels. Three are inputs to a 12-bit ADC. Two of these inputs can be configured as outputs by enabling 10-bit DACs. The other two channels are dedicated outputs from two independent 12-bit DACs.

The high level of integrated functionality, small size, and low power dissipation of the AD9961/AD9963 make them well- suited for portable and low power applications.

APPLICATIONS

• Wireless infrastructure Picocell, femtocell basestations
• Medical instrumentation Ultrasound AFE
• Portable instrumentation Signal generators, signal analyzers

The AD9961/AD9963 are pin-compatible, 10-/12-bit, low power MxFE^® converters that provide two ADC channels with sample rates of 100 MSPS and two DAC channels with sample rates to 170 MSPS. These converters are optimized for transmit and receive signal paths of communication systems requiring low power and low cost. The digital interfaces provide flexible clocking options. The transmit is configurable for 1×, 2×, 4×, and 8× interpolation. The receive path has a bypassable 2× decimating low-pass filter.

The AD9961 and AD9963 have five auxiliary analog channels. Three are inputs to a 12-bit ADC. Two of these inputs can be configured as outputs by enabling 10-bit DACs. The other two channels are dedicated outputs from two independent 12-bit DACs.

The high level of integrated functionality, small size, and low power dissipation of the AD9961/AD9963 make them well- suited for portable and low power applications.

APPLICATIONS

• Wireless infrastructure Picocell, femtocell basestations
• Medical instrumentation Ultrasound AFE
• Portable instrumentation Signal generators, signal analyzers

The AD9081-FMCA-EBZ evaluation board includes all of the support circuitry required to operate the AD9081 in various modes and configurations. The application software used to interface with the device is also described. The AD9081-FMCA-EBZ evaluation board connects to the Analog Devices, Inc., ADS9-V2EBZ for evaluation with the ACE software. The boards can also interface to commercially available field-programmable gate array (FPGA) development boards from Xilinx® or Intel^®. Information on how to use these platforms to evaluate the AD9081 or AD9082 is available in the Using the AD-FMC-SDCARD section.

The ACE software allows the user to set up the AD9081 or AD9082 in various modes, and capture analog-to-digital converter (ADC) data for analysis. The DPGDownloaderLite software generates and transmits vectors to the DACs, which can then be sent to a spectrum analyzer for further analysis. For more details, see the AD9081 and AD9082 data sheets, which must be consulted in conjunction with this user guide when using the evaluation boards.

The AD9082-FMCA-EBZ evaluation board includes all of the support circuitry required to operate the AD9082 in various modes and configurations. The application software used to interface with the device is also described. The AD9082-FMCA-EBZ evaluation board connects to the Analog Devices, Inc., ADS9-V2EBZ for evaluation with the ACE software. The boards can also interface to commercially available field- programmable gate array (FPGA) development boards from Xilinx^® or Intel^®. Information on how to use these platforms to evaluate the AD9081 or AD9082 is available in the Using the AD-FMC-SDCARD section.

The ACE software allows the user to set up the AD9081 or AD9082 in various modes, and capture analog-to-digital converter (ADC) data for analysis. The PGDownloaderLite software generates and transmits vectors to the DACs, which can then be sent to a spectrum analyzer for further analysis. For more details, see the AD9081 and AD9082 data sheets, which must be consulted in conjunction with this user guide when using the evaluation boards.

The user guide describes the AD9081-FMCA-EBZ, AD9082-FMCA-EBZ, AD9986-FMCB-EBZ, and AD9988-FMCB-EBZ evaluation boards, which provide all of the support circuitry required to operate the AD9081, AD9082, AD9986, AD9988, AD9207, AD9209, or AD9177 in their various modes and configurations. The application software used to interface with the devices is also described. These evaluation boards connect to the Analog Devices, Inc., ADS9-V2EBZ for evaluation with the ACE software.

These evaluation boards can also interface to commercially available field-programmable gate array (FPGA) development boards from Xilinx^® or Intel^®. Information on how to use these platforms to evaluate the AD9081 or the AD9082 is available in the Using the AD-FMC-SDCARD section.

The ACE software allows the user to set up the MxFE^® in various modes and to capture analog-to-digital converter

For additional information, see the AD9081, AD9082, AD9986, AD9988, AD9207, AD9209, or AD9177 data sheets and the UG-1578, the device user guide, which must be consulted in conjunction with the user guide when using the evaluation boards.

The user guide describes the AD9081-FMCA-EBZ, AD9082-FMCA-EBZ, AD9986-FMCB-EBZ, and AD9988-FMCB-EBZ evaluation boards, which provide all of the support circuitry required to operate the AD9081, AD9082, AD9986, AD9988, AD9207, AD9209, or AD9177 in their various modes and configurations. The application software used to interface with the devices is also described. These evaluation boards connect to the Analog Devices, Inc., ADS9-V2EBZ for evaluation with the ACE software.

These evaluation boards can also interface to commercially available field-programmable gate array (FPGA) development boards from Xilinx^® or Intel^®. Information on how to use these platforms to evaluate the AD9081 or the AD9082 is available in the Using the AD-FMC-SDCARD section.

The ACE software allows the user to set up the MxFE^® in various modes and to capture analog-to-digital converter

For additional information, see the AD9081, AD9082, AD9986, AD9988, AD9207, AD9209, or AD9177 data sheets and the UG-1578, the device user guide, which must be consulted in conjunction with the user guide when using the evaluation boards.

When connected to a specified Analog Devices high speed converter evaluation board, the ADS8-V3EBZ works with ADI evaluation software as a data capture/transmit and control interface. Designed to support high speed data converters with JESD204B/C serial line rates up to 16.375 Gbps, the FPGA on the ADS8-V3EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.

Limited to use cases where lane rates are less than 16.375 Gbps due to the FPGA capability. (Applies to AD9081 and AD9082.)